The disclosure relates to a method for fabricating a semiconductor device, and more particularly, to a semiconductor device with a strained channel and a method for fabricating the same.
As the integration of semiconductor devices continues to increase, the channel lengths of metal oxide semiconductor (MOS) devices continue to be reduced. The reduction in a channel length increases carrier mobility, i.e., hole or electron mobility, and thus an operation speed and operation current of a semiconductor device also increases.
However, the reduction in a channel length brings about a short channel effect (SCE) such as a decrease in a threshold voltage. If an impurity doping concentration increases to overcome the short channel effect, an impurity scattering of carriers into a channel or channels also increases, resulting in a decrease in carrier mobility. Accordingly, the operation speed and operation current of a device is reduced.
Therefore, various methods of increasing carrier mobility by inducing a strain in the channels has been proposed to improve the operation speed and operation current of a semiconductor device. Among these methods, much attention has been paid to a method of forming a strained channel, which includes forming a recess pattern in a region for a source and a drain around sidewalls of a gate pattern, filling the recess pattern with an epitaxial layer formed of a Group IV element having different lattice constant from that of silicon, and applying a stress to the channel.
FIG. 1 illustrates a cross-sectional view of a typical semiconductor device with a strained channel.
Referring to FIG. 1, a gate pattern 13 is formed on a silicon substrate 11, and gate spacers 14 are formed on both sidewalls of the gate pattern 13. At both sides of the gate pattern 13, recess patterns 12 are provided in the silicon substrate 11 where a source S and a drain D will be formed. Epitaxial layers 15 are formed to fill the recess patterns 12 through selective epitaxial growth (SEG). A strained channel C is formed in the silicon substrate 11 between the recess patterns 12. The epitaxial layers 15 are formed of a material having a different lattice constant from that of the silicon substrate 11, and serve as the source S and the drain D. For example, the epitaxial layer 15 is an epitaxial silicon germanium (SiGe) layer or an epitaxial silicon carbon (SiC) layer.
To effectively induce a strain in the channel C in the typical semiconductor device, a method of increasing a volume of the epitaxial layer 15 by increasing a depth of the recess pattern 12, or a method of increasing a difference in lattice constant between the silicon substrate 11 and the epitaxial layer 15 by increasing the concentration of germanium or carbon in the epitaxial layer 15, is employed.
However, the increase in the depth of the recess pattern causes a growth thickness of the epitaxial layer 15 to be increased, leading to a reduction in productivity of devices. Furthermore, due to a critical thickness of the epitaxial layer 15 allowing the epitaxial layer 15 to grow without a defect through the SEG, the layer quality of the epitaxial layer 15 is reduced as the growth thickness of the epitaxial layer 15 is increased.
Moreover, if the concentration of germanium or carbon in the epitaxial layer 15 increases, the critical thickness allowing the epitaxial layer 15 to grow without a defect through the SEG is reduced and therefore reduces the quality of the layer.